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Nepes Semiconductor R&D Center performs intensive research on WLP, Fan-out WLP and Sip for the purpose of making lighter and more functional devices on the basis of wafer redistribution, Bumping and PKG Back-End Processing Technology
WLP refers to the technology of packaging an integrated circuit at wafer level, instead of the traditional process
Fan-out wafer level technology offers the ability to provide a higher number of interconnects than is possible with fan-in
wafer level technology
SiP is more than a just ordinary IC package containing multiple die