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BUSINESS

GLOBAL TOP-TIER PARTNER, NEPES

Fan Out-WLP/PLP

입출력(I/O) 단자를 칩 바깥으로 재배열하여
칩을 보다 작게, 고성능으로 구현할 수 있는 미세 패키징 솔루션입니다.

FOWLP/nPLP™ Solutions

To provide multiple package solutions, high reliability and functionality in a smaller footprint for expanding the portfolios

Fan-Out packaging is the platform with expanded connections out of the chip area, enabling more external I/Os.

FOWLP & M-series™ based (300mmRd) and PLP (600mmSq) with test & Back-end turnkey service

nPoP™ Solutions

nPoP™(nepes Package of Package), both in Chip-first & Chip-last platform, is a Fan-out based stacking package

It combines a FO bottom on which a memory is mounted, and includes Cu posts for through-mold vertical interconnections.

Product View

VALUE FOWLP RCP™ FOWLP/PLP M-Series™ PoP
300mm Round 300mm Round 600mm Panel Chip-First Chip-Last
Product View
Advantages

FOWLP is conventional fan- out
WLP with molding & wafer level
RDL technology

Smaller form-factor, Thinner profile
and substrate-less package

Higher electrical performance with
lower transmission loss of shorter
electrical path

With M-Series and Adaptive Patterning®,the barriers to chips-first,
high-density fan-out disappear

Die shift and warpage control through Adaptive patterning 6 sides protection
for Higher board level reliability with M-Series

PLP (600mm Panel) is a technology that can utilize the area more efficiently
than the 300mm Round Panel. Fit 5x more 300mm wafers in one panel
through 600mm panel size

Very thin package profile even package stacking platform of Process
& Memory packages. The smallest Form factor (smaller size & thinner profile)

Highly integration with multi-layer RDLs and finer line & space pitch of
5um. Stackable package through Cu Post vertical interconnection technology

Higher Electrical & Thermal Performance compared to conventional PoP
packages with very shortest electrical path and higher ration of silicon
chip inside bottom package.

Features

High Reliability

Meets JEDEC MSL3 CLR and BLR
requirements

Slim & Small formfactor

Integration & Size with SiP

High Reliability

Meets JEDEC MSL3 CLR and BLR requirements

Slim & Small formfactor

Flexible productivity

Cost effectiveness

Attributes: Package & Die Size:
14mmX15mm & 12mmX11mm

IO: ~1500 Backside 2-RDL(8um L/S)

Frontside 3-RDL(5um L/S)

Cu Post 90um CD, 60um Space

Package size : 14mm x 15mm

Package thickness : 310um
( 230um w/o BGA )

Chip size : 10.9mm x 11.7mm

Double side RDL : Front-side(4P4M ),
Back-side( 3P3M )

Cu-post pitch : 150um,
Cu-post height : 160±10um

Fine-pitch RDL : L/S=5/5um,
Min. via diameter=Ø15um

Min. chip pad pitch : 90um

Application Communication, Consumer, Automotive, Industrial, Computer,
(RF, PMIC, AP, Connectivity, Baseband, Audio codec, sensor, (x)PU)

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nepes laweh

Address충청북도 괴산군 청안면 네패스로 30

Tel043) 240-0500(내선3번)

E-mailsales@nepes.co.kr

nepes hayyim

Address100 East Main Ave. Laguna Technopark Biñan, Laguna, Philippines 4024

Tel+63-2-7902-5600

E-mailsales@nepes.co.kr