“Heterogeneous integration,” a hot keyword in the global semiconductor market
Nepes’s fan-out technology-applied “nSiP” & “nPoP” are the alternatives
The global semiconductor industry started to focus on the back-end process. As Moore’s law, which states that the semiconductor density doubles every two years, is no longer valid, and miniaturization of circuits in the front-end process is reaching its limit, the industry players are looking for alternatives. Among the alternatives, the “Heterogeneous Integration Packaging,” also referred to as a 2D and 3D packaging has been gaining attentions as the next-generation technology. It attaches chips in series and integrates them to a single semiconductor piece.
On July 7th,Nepes introduced its unique technology “nSiP’ and “nPoP” along with the trends of the next-generation heterogeneous integration packaging at “Semiconductor Packaging Day 2022” held by Electronics Times, a Korean IT news media.
Nepes is an advanced semiconductor packaging company that supplies the Wafer Level Packaging(WLP), Fan-Out Panel Level Packaging(FOPLP) and more.
It is a pioneer in the back-end process as it commercialized the FOPLP technology for 600x600mm square panels, not round panels, for the first time in the world in May 2017.
System in Package(SiP) introduced by Nepes at the conference, is a heterogeneous integration packaging technology with various functions put into a single chip. Nepes’s unique technology “nSiP” does not contain components such as substrates, reducing the packaging size to one third and shortening the signal transmission distance by 30% for performance improvement. Nepes produced its first commercialized nSiP in January.
Package on Package(PoP) is a technology that adds a layer of package with a different function on top of another package. This technology minimizes heat generation from the chips and lowers the packaging thickness by 26% compared to competitors’ products. Mass production is scheduled to be in 4Q, 2023.
Nepes’s unique packaging technologies are based on the Fan-Out technology that utilizes the Re-Distribution Layer(RDL). In the Fan-Out technology, the input/output terminals are located outside the chips to fit in a higher number of terminals. It is expected to be the solution for the ultra-high-performance and high-integration packaging market since it can be used to layer or expand different sizes of chips as well as to improve the electrical properties and thermal efficiency,
In the meantime, the global packaging market size is expected to be driven by the SiP, Fan-Out, and PoP technologies and reach a $9.6 billion scale by 2026 according Yole, a market analysis firm. The PoP’s market share is expected to increase particularly high from 5% to 11%.