- NEWS
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[DIC2024] Nepes Increases Production and Reduces Costs for FO Packaging
Jong Heon Kim, head of Nepes' Technology Development Division, gives a presentation on 'Trends and Role of Advanced Packaging Technology in High Performance Products' at the '2nd DigitalDaily Industry Conference (DIC) 2024', held from 1:00 p.m. on November 21st at the Yeouido FKI Tower Conference Center Diamond Hall in Seoul, Korea .[DigitalDaily reporter Kim Moon-ki] “Our continued efforts in packaging for the production of semiconductors in the AI era aim to increase production capacity. Nepes strives to bring not only productivity but also price competitiveness through fan-out (FO) packaging technology to silicon interposer. We will provide multiple services on a two-track basis, including technologies that cover 2.5D packaging and hold multiple chips in one package.”Jong Heon Kim spoke about Nepes' competitiveness on the topic of 'Trends and Role of Advanced Packaging Technology in High Performance Products'. “The current semiconductor market resembles a war more than a strategy. As the market gradually localizes, we must focus on our strengths,” Kim said, adding that ”the same is true for the advanced packaging field.”The pressure to follow Moore's Law is on, he notes. The curve of Moore's Law, which requires a doubling of scale every two years, has been bent. It costs around $500 million to design and test an existing chip and $30-40 million to produce a single wafer. Difficulties in manufacturing and prolonged periods of development, along with the high cost are proving to be a challenge. “Packaging is the answer to physical limitations, manufacturing difficulties, and cost reduction,” said Kim. ”If there is a best practice in the construction of existing SoCs, we should follow it. Currently, chiplets are on the rise, as they can be divided by functions, in which simple processes and difficult processes are separated and put back together in the later stage of production."Kim, however, points out that while silicon intensifiers offer high performance and efficiency in 2.5D packaging, they can be costly. An alternative is fan-out (FO) and wafer-level package (WLP) technology, which Nepes focuses on. This technology involves packaging chips on a wafer-by-wafer basis. It is advantageous for cost reduction as it eliminates the need for printed circuit boards (PCBs) and reduces the number of processes.<source=nepes corp.><source=nepes corp.>Kim also emphasized the need to foster the entire cycle of production from Front-end process to Back-end process.“Even if the process is broken down into chiplets and put back together again, chip design and packaging must work together organically," he said. “In other words, it is important to build an ecosystem where the front and back are connected. In the end, the packaging and the chip must be designed together,” he said.“It is said that Korea's competitiveness requires reviewing packaging from its beginning stage. We believe that there is potential and possibility to foster a whole ecosystem of AI semiconductors because we have AI data, foundries, and data-based platform companies," he said, adding, "Korea is also in dire need of technology collaboration." [Source = DigitalDaily [DIC2024] 김종헌 네패스 “FO 패키징 ‘생산증가 원가절감’…韓 디자인-패키징 공급망 강화해야” - 디지털데일리]
2024-11-25 -
Nepes Participates in IMSP 2024
Nepes participates in the International Symposium on Microelectronics and Packaging (ISMP), an international conference dedicated to the latest trends in semiconductor packaging technology. The 22nd ISMP, organized by the Korea Society of Microelectronics and Packaging, is held on November 6-8 at the Paradise Hotel in Busan, and is co-hosted with the 18th International Conference Reliability and Stress-Related Phenomena in Nanoelectronics(IRSP).On November 6-7, Nepes will introduce its core technologies, including chiplet and 2.3D technologies, at Lobby Booth 2. On November 6 at 3:50 p.m., Nepes Semiconductor Research Center's Advanced Technology Part Leader Lee Jung Won will present on the topic of “Chip-let Heterogeneous Integration Packaging Based on Fan-out RDL Interposer Technology”.
2024-11-06 -
Nepes Holds 34th Founding Anniversary Celebration
Nepes celebrated its 34th founding anniversary on October 24th. Nepes held the ceremony from 8:30 a.m. with a worship service of thanksgiving, a commemorative video screening, a message from the CEO, and a special music class. All employees participated online and offline to share in the celebration. Afterwards, Nepes held various commemorative events such as long-term service awards for each campus, autumn hikes, and a gratitude bazaar.“For 34 years, our company has been able to grow steadfastly in the face of numerous challenges. This is thanks to our shared dreams and visions, and your dedication to doing your best in your respective positions,” said Byung Koo Lee, CEO of the company. “We have the DNA to turn turbulent external environments into opportunities for revitalization,” he said, encouraging employees that "Here at Nepes, we are the superstars who strive to be the ’The First of Yesterday and the Best of Tomorrow'".Lee also said, “To make another 34 years of expectation and excitement into an opportunity to rebound, we must first create synergy by inspiring a sense of mission in what we do. Second, we must fulfill our business plan goals with a sense of responsibility and vocation. Third, we will create an energetic and exciting work environment”.
2024-10-25 -
Nepes Kim Jong Heon Lectured advanced semiconductor packaging at 'Nano Korea 2024 Industrialization
▲Kim Jong-heon, Vice President, Lecture at the 2024 Industrialization Session of Nano KoreaNepes gave a lecture on advanced semiconductor packaging technology at 'Nano Korea 2024 Industrialization Session' held at KINTEX 1st exhibition hall in Goyang City on the 4th.Kim Jong-heon, vice president of Nepes CTO, said, "The advanced packaging technology in AI era; Chiplet and Integration ', introduced chiplet and heterogeneous packaging technology, a cutting-edge semiconductor packaging trend.Nano Korea is one of the world's top three nanotechnology events, hosted by the Ministry of Trade, Industry and Energy and the Ministry of Science and ICT, and organized by the Nano Convergence Research Association and the Nanotechnology Research Council. Among them, the industrialization session is a program that domestic and foreign global companies announce in-depth about the direction of their nanotechnology commercialization, and invited nine speakers of next-generation semiconductor and display industries, including Nepes, Samsung Electronics and SK Hynix, to give lectures.Vice President Kim Jong-heon said, "The development of Gen AI is accelerating changes in many fields such as life and industry," and explained, "In the packaging field as well as the entire semiconductor process, AI semiconductor-oriented bumping, 2.5D, and chiplet technologies continue to develop, and Nepes also has and develops related technologies and is pushing for commercialization."He added, "In addition to packaging technology, heat dissipation performance, which is closely related to power consumption, is also becoming important." He emphasized the importance of developing innovative materials along with package structure design.Meanwhile, Nano Korea is a high-tech exhibition that can confirm the commercialization status of nanotechnology and roadmap of famous domestic and foreign companies. 400 companies from 40 countries participated and 12,000 people visited.
2024-07-08 -
Nepes Participates in the 2024 ECTC
Nepes participated in the 2024 Electronic Components and Technology Conference (ECTC) in Denver, Colorado, USA from May 28 to 31 (local time) to showcase advanced semiconductor packaging technology.Celebrating its 74th anniversary this year, the 2024 ECTC is an international event hosted by the IEEE-affiliated Electronics Packaging Society and boasts the world's largest electronic component technology society.Nepes presented a 600mm FOPLP solution and a chipset packaging based on a fan-out RDL interposer at the event.On the next day of the event, the technical program participated in the announcement of advanced packaging technology with Samsung Electronics and SK Hynix as Korean companies.Nepes introduced the excellence of FOPLP as a replacement for the traditional package QFN, titled '600mm x 600mm Fan-Out Panel Level Package (FOPLP) as an Alternative to Lead-Frame-Free Quad Flat No Lead (QFN) Package'.In the Interactive Presentations session held on the same day, I also presented my thesis on 'Single and Multi NPU Chiplet Heterogeneous Integration Packaging Based on Fan-Out RDL Interposer with Silicon Bridge Technology'.
2024-06-03 -
Nepes pushes for commercialization of AI semiconductor packaging
Nepes has developed next-generation packaging PoP (Package on Package) technology for artificial intelligence (AI) and advanced semiconductor, and is working with domestic and foreign chip manufacturers to commercialize it.Recently, as the AI package market has been struggling with the global supply chain due to the oligopoly of Taiwanese companies, Nepes has developed and commercialized PoP technology, which is the base technology of 2.5D packaging *, utilizing its strengths, RDL technology.* 2.5D packaging: A technique for horizontally matching a semiconductor die on a wide substrate-shaped interposer, which is mainly used to integrate AI semiconductors and HBM (High Bandwidth Memory) into a single package.2.5D packaging, which is being developed by Nepes, has the advantage of price competitiveness and small form factor by implementing a rewiring (RDL) interposer using a fan-out process instead of an expensive silicon (Si) interposer.In particular, the developed PoP technology includes element technologies such as semiconductor device embedding technology, double-sided rewiring (RDL) technology, and Vertical Interconnection. It is a basic platform technology of advanced packaging that can expand its use to smartphone and automobile AP (Application Processor), wearable sensors, and AI semiconductors.Kim Jong-heon, chief executive officer of Nepes CTO, has been awarded "excellent performance by a global semiconductor company in Japan, a manufacturer of LiDAR sensors, which is a core technology for autonomous car, and is in the process of negotiating product applications. We are actively discussing commercialization. And based on the PoP technology developed this time, we will concentrate on 2.5D packaging technology for AI semiconductors and complete development with customers in the first half of 25 years and aim to mass-produce from the second half."Nepes is a strategic market that drives next-generation growth and aims to enter the commercialization of 2.5D and PoP technologies from the second half of 2025 by actively collaborating with AI server, automobile and edge computing product customers.press release inquiry : pr@nepes.co.kr
2024-05-20 -
Nepes wins massive PMIC orders for AI semiconductors
Nepes Semiconductors has announced that it has won a large number of low-power PMICs for AI servers from Seattle-based power semiconductor specialist fabless.The 8-inch is currently 3,000 wafers per month, but it will be increased to 20,000 wafers from the second quarter, and the 12-inch will secure production capacity of 10,000 wafers per month by this year and expand to 15,000 wafers per month by next year. The total investment is about 60 billion to 70 billion won.In particular, 12-inch products will be mainly supplied to the largest AI semiconductor server system in the United States, with up to 3,000 PMICs per system. As a result, low-power PMIC has been attracting much attention as a technology that maximizes the power efficiency of the server, and Nepes successfully commercialized this technology and won a large number of orders this time.Meanwhile, the Nepes Semiconductor division is continuing to grow significantly thanks to the growth of AI phones, and its existing business is continuing to grow steadily as OLED adoption increases in mobile phone and automotive electronics products.The Nepes Corp. has a semiconductor division and an electronic materials division, and the semiconductor division is expected to grow rapidly from 350 billion won in sales this year thanks to the growth of AI semiconductors and expect sales of more than 520 billion won in 2026, while the electronic materials division expects sales of more than 190 billion won in 2026 from 95 billion won this year. The Nepes Corp. expects sales of the two divisions to grow steeply over the next two years by forecasting sales of 445 billion won this year to 710 billion won in 2026.press release inquiry : pr@nepes.co.kr
2024-04-15 -
nepes corporation expands IC packaging capabilities for the 3DIC era with advanced design flows from
Siemens Digital Industries Software today announced that South Korea-based nepes corporation, a global leader in Outsourced Semiconductor Assembly and Test (OSAT) services, has leveraged a range of industry-leading solutions from Siemens EDA to tackle the broad range of complex thermal, mechanical, and other IC packaging design challenges associated with developing advanced 3D IC packages.“nepes is committed to providing us with the most comprehensive portfolio of semiconductor packaging design and manufacturing services, to help us innovate and succeed in a market where high performance and compact form factors are critical.” said Brad Seo, vice president of SAPEON Korea’s R&D center. “By expanding nepes’ adoption and usage of Siemens’ EDA technologies for advanced packaging, we also can achieve the innovative technologies necessary to grow.”nepes has an established track record of providing customers with world-class packaging, testing, and semiconductor assembly services for clients throughout the global electronics industry. nepes also offers packaging design services including wafer level packaging, fan-out wafer level packages, and panel level packaging.Building on this foundation, nepes is now driving additional packaging innovation with a broad range of advanced technologies from Siemens EDA, including the Calibre® nmPlatform tool, HyperLynx™ software for electrical rule checking, Calibre® 3DSTACK software, as well as Siemens’ industry-leading Xpedition™ Substrate Integrator software and Xpedition™ Package Designer software. Together, these Siemens technologies helped nepes provide fast and reliable design services including 2.5D/3D-based chiplet designs for the company’s growing base of global IC customers....Read more : https://www.eejournal.com/industry_news/nepes-corporation-expands-ic-packaging-capabilities-for-the-3dic-era-with-advanced-design-flows-from-siemens/
2024-03-19 -
Nepes enters the packaging market for AI
Due to the explosive growth of the generative artificial intelligence market such as Chat GPT, demand for advanced packaging of power semiconductors(PMIC) used in artificial intelligence systems is exploding.The product that Nepes has won this time and is starting to mass-produce is a power semiconductor for AI chipsets and a high-tech PMIC product that will expand into high-performance computing (HPC) and automobile markets in the future.Nepes has established a bridgehead for global HPC and automobile markets, starting with mass production of power semiconductors by Global Fabless (US). This new customer is a member of the value chain of AI products and is working with Nepes in a strategic partnership to prepare for explosive growth.Nepes is developing a number of its customers' products in its advanced packaging line, and it is confirmed that PMIC first shipped last year is installed in AI chipsets of GPUs, CPUs, consumers and IoT companies. Also, The product is expected to be adopted for ADAS for automobiles.In addition, the two companies are currently collaborating on a 12-inch project and plan to develop products using the 600mm PLP process in the future, diversifying their products and processes and securing competitive advantage in the market.As semiconductor manufacturing bases have recently accelerated their departure from China and Taiwan, strategic partnerships with global chipmakers and Nepes are expected to become more robust. Nepes will take this opportunity to increase its market share and continue to secure 2.5D / 3D capabilities, the next generation package for artificial intelligence.A Nepes official said, "Nepes currently has core customers mainly in the smartphone market, and this strategic partnership with new customers has enabled us to target the growing HPC and automotive markets. From an industrial point of view, It will contribute to the structural growth of non-memory manufacturing ecosystems such as foundry and tests, strengthening advanced packaging infrastructure in Korea through attracting fabless."
2024-02-26 -
Nepes successfully develops ‘Metis’, an intelligent semiconductor for edge computing
-National project successfully completed... Optimization of manufacturing inspection equipment Deep learning acceleration IP development ▲Intelligent semiconductor ‘Metis’ for edge computing equipped with deep learning acceleration IPNepes (CEO Byeong-gu Lee), a cutting-edge semiconductor back-end process foundry company, announced on the 27th that it had succeeded in developing ‘METIS’, an intelligent semiconductor for edge computing.In April 2021, Nepes Artificial Intelligence Research Institute was selected as the 'Development of Intelligent Edge Computing Semiconductor for Lightening Manufacturing Inspection Equipment' project in the 'Artificial Intelligence Semiconductor Application Technology Development Project' hosted by the Institute for Information and Communication Planning and Evaluation (IITP) under the Ministry of Science and ICT in April 2021. was selected as the host company and conducted research through an industry-academia-research consortium with the Korea Institute of Electronic Technology and Hanyang University.The researchers developed a deep learning model for ultra-lightweight/ultra-precision manufacturing inspection equipment based on an automatic lightweight software framework with the research goal of ultra-lightweight/miniaturization, low-power consumption, and low-cost of existing server- or PC-based manufacturing inspection systems. Furthermore, using this, a deep learning acceleration IP optimized for data reuse and parallel computing processing was completed and installed on Metis.As a result, Nepes has developed a neural network-based deep learning defect detection algorithm that can reorganize the existing server-centered AI system into a terminal-centered one, and has secured a low-power SoC platform technology that reflects this. Through technological advancement, it has been able to increase productivity and efficiency at the manufacturing site. We hope to be able to contribute.In addition, Metis applied cx-BGA (Ball Grid Array) of nePACTM, Nepes' cutting-edge 2.5D & 3D package platform. nePACTM is a next-generation cutting-edge package technology that implements multi-layer and fine RDL wiring based on fan-out technology and flip chip bonding technology, and is suitable for highly integrated, high-performance chips such as artificial intelligence semiconductors.Yeonsook Park, head of Nepes Artificial Intelligence Research Center, said, “Through this research, we will solve network traffic issues in existing cloud server-type systems and secure intelligent processor technology that can detect defects at the edge, thereby developing various deep learning-related applications needed throughout the industry. “We have been able to accelerate it,” he said.Meanwhile, Nepes is carrying out national projects to develop core packaging technologies for system semiconductors and AI semiconductors, such as 'Development of chiplet heterogeneous integration ultra-high-performance artificial intelligence semiconductors' with a total project cost of KRW 44 billion hosted by the Ministry of Science and ICT, as well as AI semiconductors specialized for on-device. We are working to secure original technology.
2023-12-27 -
Nepes announces interim results of mobile self-learning processor national project
-Introducing artificial intelligence semiconductors equipped with self-learning NPU IP-Securing source technology to advance on-device AI semiconductor technology ▲ Nepes participated in the 2023 Artificial Intelligence Semiconductor Future Technology ConferenceNepes(CEO B.K. Lee), a cutting-edge semiconductor back-end process foundry company, presented interim results of the artificial intelligence (AI) semiconductor research and development national project at the ‘2023 Artificial Intelligence Semiconductor Future Technology Conference’ hosted by the Ministry of Science and ICT on the 19th This event is held every year, hosted by the Ministry of Science and ICT and organized by the Artificial Intelligence Semiconductor Forum, the Next-Generation Intelligent Semiconductor Business Group, and the Information and Communication Planning and Evaluation Institute to develop the AI semiconductor industry. In addition to exhibiting the AI semiconductor development achievements of participating companies, the Ministry of Science and ICT and domestic and foreign experts provide industry advice. We provide an opportunity to announce and discuss technology trends and major policy trends. At this event, which marks its 4th anniversary this year, Nepes exhibited 'JANUS', which has a mobile self-learning neural network processing unit (NPU) IP for object classification, and a distributed learning IP driving system. In particular, ‘Janus’ is a lightweight self-learning NPU IP-embedded artificial intelligence semiconductor developed to meet the needs of the market where the need for ‘on-device learning’ for optimal reconstruction (relearning) of artificial intelligence models in user development environments is emerging. This has a wide range of application fields, from intelligent automobile systems such as smart keys and driver monitoring systems through new user authentication to intelligent factory fields such as field learning systems to improve defect recognition rates.In April 2020, Nepes was selected as the lead organization for the ‘Development of mobile self-learning recursive neural network processor technology’ project in the ‘Next-generation intelligent semiconductor technology development project’ hosted by the Ministry of Science and ICT and is carrying out five years of research. This study aims to secure core technologies that enable lightweight semi-supervised learning and distributed learning by equipping devices with learning functions to optimize the privacy of personal and security data and the user environment. Many institutions, including Chungbuk National University, Hanyang University, and Seoul National University of Science and Technology, are collaborating. Based on its AI design technology, Nepes has not only secured on-device specialized AI semiconductor source technologies such as ‘mobile self-learning’ and ‘AI semiconductor lightweight’, but also developed on-device AI integrated platform technology. ▲ AI Chip with built-in lightweight self-learning NPU IP“The on-device AI semiconductor market is blooming, and in particular, AI semiconductors that can learn at the device level have endless applications in our daily lives,” said Park Yeon-sook, head of Nepes. “The result of this project is the development of on-device AI technology.” “It will secure fundamental technology for advancement,” she said. In addition, Nepes is developing its own cutting-edge technologies, such as 'Development of chiplet heterogeneous integration ultra-high-performance artificial intelligence semiconductor' with a total project cost of KRW 44 billion hosted by the Ministry of Science and ICT, and 'Development of core materials and process technology for 3D IC manufacturing using FOWLP' hosted by the Ministry of Trade, Industry and Energy. Based on packaging manufacturing technology, we are carrying out various national projects to develop core technologies for system semiconductor and AI semiconductor packaging.
2023-12-19