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R&D

NEPES, GLOBAL TOP-TIER PARTNER

Leading the new era with
 cutting-edge  semiconductor  packaging solution 

FOPLP
FOPLP 이미지
  • 3D PoP Stackable( mPoP ) 이미지

    3D PoP Stackable( mPoP )

  • PoP( Package on Package ) 이미지

    PoP( Package on Package )

  • Multi-die( 2die ) 이미지

    Multi-die( 2die )

  • Chip-first( Face-up ) 이미지

    Chip-first( Face-up )

  • Chip-first( Face-down ) 이미지

    Chip-first( Face-down )

  • A leading technology for next generation in the field of packaging
  • Providing the high performance required for the 4th industrial revolution, including 5G and cloud data services
  • Utilizing large square panel process in order to innovative productivity improvement and cost reduction beyond fan-out WLP process
  • Advanced fan-out packaging technologies (MCP, mPoP, PoP) applicable to various markets and products, such as PMIC, RF module, APE, and memory
3D-SiP
3D-SiP 이미지
  • Multi-die stack solution based on the fan-out method for high bandwidth and high-function devices in the age of 5G and AI
  • Provision of low-price/high-function products using fan-out wiring technology and via formation technology, not the platform of TSV and Interposer
  • With the creation of 2.5D and 3.D solutions, it is applicable to high-end computing packaging product combining high bandwidth memory and NNP
FOWLP/WLP
  • nWLPRB 이미지

    [nWLPRB]

  • nWLPHR 이미지

    [nWLPHR]

  • nWLPHC 이미지

    [nWLPHC]

  • FOWLP 이미지

    [FOWLP]

  • FOWLP 이미지

    [FOWLP]

  • FOWLP 이미지

    [FOWLP]

  • Creation of high-reliability, high-current WLP solution based on the differentiated technology of nepes
  • Applicable to products in the fields of automotive, aerospace, and military along with the cutting-edge IT industry