Nepes participated in the IEEE Electronics Packaging Technology Conference (EPTC 2025), held in Singapore from December 2 to 5, and presented its research results under the theme “Development of Embedded Bridge Die Interposer Using Fan-out Packaging for Heterogeneous Integration of NPUs and HBMs.”

EPTC is a prestigious international conference in the Asia-Pacific region on semiconductor packaging and heterogeneous integration, organized by the IEEE Electronics Packaging Society (EPS). Leading global semiconductor companies and research institutions such as ASE, Amkor, TSMC, IMEC, and A*STAR take part in this event to share the latest technology trends.

The presentation addressed the growing need to densely integrate NPUs and HBMs within a single package for HPC and AI systems, introducing an Embedded Bridge Die Interposer technology based on FOWLP (Fan-Out Wafer Level Packaging) to overcome the limitations of conventional silicon interposers. The institute showcased its in-house developed process flow, including wiring formation and die bonding, along with prototype samples, highlighting the scalability of fan-out technology.

This year’s conference mainly featured topics on heterogeneous integration technologies, including hybrid bonding, and materials, providing insights into the global research and industry directions. Through this, Nepes reaffirmed the need to further strengthen follow-up process development and reliability evaluation for its ongoing 2.5D and edge computing technologies.

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